In integrated circuits (ICs), internal clock signals are usually generated by a digital controlled delay line (DCDL) of a delay-locked loop (DLL). In general, a DCDL is used to prevent an external clock signal from arriving at an output until a predetermined time has elapsed. The DCDL typically contains several delay cells, with each of the delay cells having a corresponding delay time. The total delay time of the DCDL can be set by increasing or decreasing the number of delay cells that a signal passes through. To achieve finer granularity of delay-time adjustment, the DCDL includes a huge amount of delay cells that can be adjusted.